1. Field of the Invention
The present invention relates to a semiconductor circuit device, and more particularly to a semiconductor circuit device referred to as a system LSI having memory and logic integrated on the same semiconductor substrate. More particularly, the present invention relates to the configuration of externally testing an embedded memory with respect to signal/data timing conditions.
2. Description of the Background Art
A DRAM-embedded system LSI having a DRAM (Dynamic Random Access Memory) and a logic device or microprocessor integrated on the same semiconductor substrate is becoming wide-spread. The DRAM-embedded system LSI has the following advantages, different from a conventional system in which a discrete DRAM and a discrete logic device or microprocessor are mounted on a printed board with soldering or the like.
(1) Since there are no limitations by pin terminals, the width of a data bus between a DRAM and a logic device can be widened, data transfer rate can be improved, and, accordingly, system performance can be improved.
(2) A data bus between the DRAM and a logic device is formed of on-chip interconnection lines smaller in load than on-board wires. Consequently, an operation current at the time of data transfer can be decreased and data can be transferred at high speed.
(3) Since a system is formed in a single package, external data bus wiring and external control signal wiring are unnecessary, the occupation area of the system on a printed board can be reduced, and the overall system can be down-sized.
FIG. 8 is a diagram schematically showing an example of the configuration of a conventional DRAM-embedded system LSI. In FIG. 8, a DRAM-embedded system LSI 500 includes: a logic 502 for performing a predetermined operational process; a DRAM macro 504 for storing at least data required by logic 502; and a logic external bus 508 for connecting logic 502 to an external device via a pad group 518.
Logic 502 may be a logic device dedicated to perform the predetermined operational process, or may be a microprocessor. Logic 502 is merely required to perform a process using data stored in DRAM macro 504.
DRAM macro 504 includes: a DRAM core 510 for storing data; a test interface circuit (TIC) 512 for allowing an external direct access to DRAM core 510 to perform a test; and a selecting circuit 517 for selecting one of an internal logic bus 506 of logic 502 and an internal test bus 516 from test interface circuit 512 and coupling the selected one to an internal memory bus 515 in accordance with a test mode instruction signal MTEST. Internal memory bus 515 is connected to DRAM core 510. Test interface circuit 512 is coupled to pad group 518 via an external test bus 514.
Each of buses 506, 508, 514, 515 and 516 includes signal lines for transmitting a control signal, an address signal and data. Since the internal logic bus 506, internal memory bus 515, and internal test bus 516 do not suffer from limitation due to the count of pin terminals, the bus widths can be made sufficiently wide.
Read data from DRAM core 510 is transferred directly to test interface circuit 512 and logic 502, with selecting circuit 517 bypassed. However, in FIG. 8, to simplify the drawing, a transfer path of internal read data is not shown.
FIG. 8 shows both logic external bus 508 and external test bus 514 being coupled to pad group 518. Alternatively, external test bus 514 and logic external bus 508 may be selectively connected to common pads in accordance with test mode instruction signal (MTEST). In accordance with test mode instruction signal MTEST, selecting circuit 517 couples test interface circuit 512 to DRAM core 510.
FIG. 9 is a diagram showing the signals for DRAM core 510 in a list form. In FIG. 9, to DRAM core 510, a clock signal CLK is supplied as an operation timing determination signal. DRAM core 510 takes in signals/data and outputs data, synchronously with clock signal CLK.
DRAM core 510 receives, as operation control signals, a dock enable signal CKE for setting validity/invalidity of an internal clock signal in DRAM core 510, a row activating signal /ACT for activating an internal row selecting operation, a row inactivating signal /PRE for driving a selected row to a not-selected state, an auto refresh instruction signal /REFA for instructing refresh of memory cell data in DRAM core 510, a read operation instruction signal /RE for instructing reading of data, and a write operation instruction signal /WR for instructing data writing operation.
For designating an address of a memory cell, DRAM core 510 is further supplied with a 13-bit row address signal RA less than 12:0 greater than , a 4-bit column address signal CA less than 3:0 greater than , a spare row space addressing address signal RAsp for designating a spare memory cell row, and a spare column space addressing address signal CAsp for designating a spare column.
Spare row space addressing address signal RAsp and spare column space addressing address signal CAsp are used to access a spare memory cell of DRAM core 510 and determine whether the spare memory cell is defective or not in a test performed before a defect address fuse programming.
When spare space addressing address signals RAsp and CAsp are at the H level, a spare memory cell space is designated. When they are at the L level, a normal memory cell space is designated.
To DRAM core 510 is further supplied with data D less than 127:0 greater than  of 128 bits and spare write data SD less than 1:0 greater than  of two bits. From DRAM core 510, read data Q less than 127:0 greater than  of 128 bits and spare read data SQ less than 1:0 greater than  of two bits are outputted. When an address of the spare memory cell space is designated, a spare memory cell for redundancy replacement is designated. Therefore, by designating a spare memory cell by spare space addressing address signals RAsp and CAsp and writing/reading data to/from the designated spare memory cell, the spare memory cell can be tested directly from the outside of the DRAM core.
As shown in FIG. 9, DRAM core 510 has a larger number of input/output signals, as compared with a general discrete DRAM. Test interface circuit 512 generates the signals and data as shown in FIG. 9 for DRAM core 510 in a testing operation in accordance with signals applied from an external tester.
If test interface circuit 512 transmits/receives the signals/data shown in FIG. 9 to/from the external tester by external test bus 514 via pad group 518, the number of lines of the signals/data becomes larger than the number of pins of the external tester, so that a test cannot be performed. Even if a test can be performed, due to the large number of signal lines and data lines necessary for a device to be test, the number of devices which can be measured at the same time decreases, and the test cost increases.
Test interface circuit 512 is provided to reduce the number of pins required in the test and to allow a direct access to DRAM core 510 from the outside of the device to improve testability of DRAM core 510.
FIG. 10 is a diagram showing, in a list form, external signals for test interface circuit 512. The signals shown in FIG. 10 are transferred between an external tester and test interface circuit 512 via external test bus 514 shown in FIG. 8.
In FIG. 10, a test clock signal TCLK and a test clock enable signal TCKE are applied to test interface circuit 512. Test clock signal TCLK and test clock enable signal TCKE are used in a test operation mode in place of clock signal CLK and clock enable signal CKE applied to DRAM core 510 in the normal operation mode.
To test interface circuit 512, further, a chip select signal /CS, a row address strobe signal /RAS, a column address strobe signal /CAS and a write operation instruction signal /WE are applied. In accordance with a combination of logic levels, for example, at the rising edge of the test clock signal, of these control signals /CS, /RAS, /CAS and /WE, an operation mode of the DRAM core is designated.
Test interface circuit 512 decodes the external control signals and selectively activates row activating signal /ACT, row inactivating signal /PRE, auto refresh instruction signal /REFA, read operation instruction signal /RE and write operation instruction signal /WE as shown in FIG. 9 in accordance with a result of the decoding.
As an address signal, 13-bit address signal AD less than 12:0 greater than  and a spare space addressing address signal ADsp are applied to test interface circuit 512. A row address and a column address are applied in a time division multiplexed manner via the common pads (terminals). Spare space addressing address signal ADsp is also applied to a spare row and a spare column in a time division multiplexed manner.
As data, 8-bit test write data TD less than 7:0 greater than , 8-bit test read data TQ less than 7:0 greater than  and a multi-bit test result instruction signal TQmbt of one bit are transferred between the external tester and test interface circuit 512.
In writing test data, test interface circuit 512 expands the bit width of 8-bit test data TD less than 7:0 greater than  to 128-bit data and supplies the 128-bit data to DRAM core 510 via selecting circuit 517. In expanding the bit width of the test write data, by repeatedly copying 8-bit test data TD less than 7:0 greater than , 128-bit data of 16 pieces of 8-bit data of the same pattern is generated.
In reading test data, test interface circuit 512 sequentially outputs the 128-bit data read from DRAM core 510 on an 8-bit basis.
Multi-bit test result instruction signal TQmbt is a signal indicative of a result of the multi-bit test on the test read data of 128 bits. By using multi-bit test result instruction signal TQmbt, it becomes unnecessary to determine pass/fail for each of the data of 128 bits. Although the data is outputted on the 8-bit basis, by identifying a defective cell only when the multi-bit result indicates a failure, test time can be shortened.
FIG. 11 is a diagram showing, in a truth table form, the relation between the external control signals (TIC control signals) applied to test interface circuit 512 and the control signals (DRAM control signals) applied to DRAM core 510. An operation mode to be designated is indicated by a mnemonic code.
In FIG. 11, a non-selection state (DSEL) of the DRAM macro is set when chip select signal /CS is at the H level. In this state, DRAM core 510 maintains the non-selection state irrespective of the logic levels of the remaining control signals /RAS, /CAS and /WE.
When chip select signal /CS is set to the L level, an operation mode for DRAM core 510 is designated.
In the case of NOP (No Operation) designating no operation mode, all of the control signals /RAS, /CAS and /WE are set to the H level. In this case, all of the control signals applied to DRAM core 510 maintain the H level, and a new operation mode for DRAM core 510 is not designated. DRAM core 510 usually maintains a standby state when an NOP command is supplied.
When both chip select signal /CS and row address strobe signal /RAS are set to the L level and both column address strobe signal /CAS and write operation instruction signal /WE are set to the H level, ACT indicative of array activation is designated. In this state, to DRAM core 510, row activating signal /ACT is set to an active state at the L level. The remaining DRAM control signals each maintain an inactive state at the H level.
Here, the logic level of the TIC control signal for test interface circuit 512 is determined at the rising edge or falling edge of test clock signal TCLK.
When chip select signal /CS, row address strobe signal /RAS and write operation instruction signal /WE are set to the L level and column address strobe signal /CAS is maintained at the H level, PRE indicative of precharging operation is designated. In this state, row inactivating signal /PRE is set to the L level as a DRAM control signal and DRAM core 510 is reset to the precharge state.
When chip select signal /CS, row address strobe signal /RAS and column address strobe signal /CAS are set to the L level and write operation instruction signal /WE is set to the H level, REFA indicative of a refreshing operation is designated. In this case, auto refresh instruction signal /REFA from among the DRAM control signals is set to the L level, and refreshing operation is executed in DRAM core 510.
When both chip select signal /CS and column address strobe signal /CAS are set to the L level and both row address strobe signal /RAS and write operation instruction signal /WE are set to the H level, RE instructing data reading operation is designated. In this case, read operation instruction signal /RE among the DRAM control signals is set to the active, low state, and the remaining DRAM control signals are maintained at the H level.
When chip select signal /CS, column address strobe signal /CAS and write operation instruction signal /WE are set to the L level and row address strobe signal /RAS is set to the H level, WE instructing data writing operation is designated. In this state, write operation instruction signal /WR among the DRAM control signals is set to the L level.
In test interface circuit 512, in accordance with the truth table shown in FIG. 11, a TIC control signal is translated into a DRAM control signal. By performing multiplexing of addresses, conversion of the data bit width, and translation of the control signals in test interface circuit 512, the number of pin terminals used when the external tester accesses DRAM core 510 and performs a testing operation can be significantly reduced. The control signals supplied to test interface circuit 512 are the same as those used for a normal clock synchronous DRAM. Therefore, DRAM core 510 can be tested using a tester for a standard clock synchronous DRAM.
FIG. 12 is a diagram schematically showing the configuration of DRAM core 510 and test interface circuit (TIC) 512 shown in FIG. 8. In FIG. 12, selector (selecting circuit) 517 disposed between DRAM core 510 and test interface circuit 512 is not shown in order to simplify the drawing.
In FIG. 12, DRAM core 510 includes: DRAM arrays 550e and 550w each having a plurality of memory cells arranged in rows and columns; and a decoder 552 for selecting a memory cell from DRAM arrays 550e and 550w in accordance with an address signal.
Each of DRAM arrays 550e and 550w has a storage capacity of, for example, 8 M bits.
In DRAM arrays 550e and 550w, spare rows and spare columns for repairing a defective memory cell are disposed.
Decoder 552 includes both a row decoder for selecting a memory cell row in DRAM arrays 550e and 550w and a column decoder for selecting a memory cell column.
By disposing the row decoder and the column decoder in the same direction, internal multi-bit data bus lines can be laid over the memory cell arrays (DRAM arrays), so that the chip area can be reduced. The configuration of disposing the column decoder for column selection and the row decoder for row selection in the same direction is generally used for a logic-merged DRAM macro.
DRAM core 510 further includes: a DRAM data path 556e for inputting/outputting data to/from DRAM array 550e; a DRAM data path 556w for inputting/outputting data to/from DRAM array 550w; and a DRAM control circuit 558 for controlling an internal operation of DRAM core 510.
Each of DRAM data paths 556e and 556w includes: a write driver for transferring internal write data to corresponding DRAM array 550e or 550w; and a preamplifier for amplifying memory cell data read from corresponding DRAM array 550e or 550w. 
DRAM data path 556e transfers write data WD less than 127:64 greater than  via a write data bus 551e of a 64-bit width and receives internal read data RD less than 127:64 greater than  of 64 bits transferred from DRAM array 550e via an internal read data bus 553e. 
A column selection line from the column decoder provided in decoder 552 is disposed extending in the row direction. In DRAM array 550e, a spare column is selected simultaneously with a normal column. In repairing a defective column, therefore, DRAM data path 556e transfers spare write data SWD less than 1 greater than  via a spare write data line 557e and receives spare read data SRD less than 1 greater than  from a spare memory cell via a spare read data line 559e. 
Similarly, DRAM data path 556w transfers internal write data WD less than 63:0 greater than  to DRAM array 550w via an internal write data bus 551w of a 64-bit width and receives internal read data RD less than 63:0 greater than  of having a width of 64 bits from DRAM array 550w via an internal read data bus 553w. 
In repairing a defective column, DRAM data path 556w further receives spare read data SRD less than 1 greater than  read from a spare column via a spare read data line 559w and transfers spare write data SWD less than 0 greater than  to a spare column via a spare write data line 557w. 
At the time of repairing a defective column in an normal operation mode, DRAM data path 556e replaces a corresponding write data line in internal write data bus 550e with spare write data line 557e, or replaces a corresponding internal read data line in internal read data bus 553e with spare read data line 559e. Similarly, at the time of repairing a defective column in the normal operation mode, DRAM data path 556w replaces a corresponding internal read data line in internal read data bus 553w with spare read data line 559w, or replaces a corresponding internal write data line in internal write data bus 551w with spare write data line 557w. 
In a test mode for repair determination performed before programming a defect address for repairing a defective column, a normal memory cell and a spare memory cell are tested, and a test for detecting whether the spare memory cell is non-defective is performed. In a memory test for repair determination, spare read data lines 559e and 559w and spare write data lines 557e and 557w in DRAM data paths 556e and 556w transmit/receive data to/from test interface circuit 512 without replacing normal data lines.
Test interface circuit 512 includes: TIC data paths 560e and 560w provided in correspondence to DRAM data paths 556e and 556w, respectively; and a TIC control circuit 562 for transmitting/receiving test write data TD less than 7:0 greater than , test read data TQ less than 7:0 greater than  and multi-bit test result instruction signal TQmbt to/from the external tester.
TIC control circuit 562 receives control signals designating the addressing and an operation mode as shown in FIG. 10 from the external tester. However, in FIG. 12, the control signals and address signals applied to TIC control circuit 562 are not shown for the purpose of simplifying the drawing.
At the time of writing test data, TIC data paths 560e and 560w expand test write data TD less than 7:0 greater than  of eight bits to test data of 64 bits and transfer the test data of 64 bits to DRAM data paths 556e and 556w via corresponding data buses 561e and 561w, respectively.
At the time of reading data, TIC data paths 560e and 560w receive read data of 64 bits (read data of 128 bits in total) from DRAM data paths 556e and 556w via data buses 563e and 563w, respectively.
TIC data path 560e receives 64-bit data Q less than 127:64 greater than  from DRAM data path 556e via data bus 563e and also receives spare read data SRD less than 1 greater than  from spare internal read data line 559e transmitted via DRAM data path 556e, as spare data SQ less than 1 greater than  via a spare read data line 569e. 
TIC data path 560e transfers 64-bit write data D less than 127:64 greater than  to DRAM data path 556e via internal write data bus 561e, and also transfers spare write data SD less than 1 greater than  to internal spare write data line 557e via spare write data line 567e. 
Similarly, TIC data path 560w receives internal read data Q less than 63:0 greater than  from DRAM data path 556w via read data bus 563w and receives spare read data SQ less than 0 greater than  via spare data line 569w. TIC data path 560w transfers 64-bit data D less than 63:0 greater than  to DRAM data path 556w via write data bus 561w and transfers spare write data SD less than 0 greater than  to DRAM data path 556w via spare write data line 567w. 
At the time of reading data, TIC control circuit 562 sequentially outputs the data of 128 bits in total supplied to TIC data paths 560e and 560w as test data TQ less than 7:0 greater than  on an 8-bit data basis.
TIC control circuit 562 transfers the signal TQmbt indicative of a result of the multi-bit test on the 128-bit data simultaneously read via multi-bit signal line 573. When multi-bit test result indication signal TQmbt indicates mismatch, in the external tester, a defective memory cell is identified on the basis of test read data TQ less than 7:0 greater than  and expected value data.
FIG. 13 is a diagram schematically showing the configuration of a part related to data writing of TIC data paths 556e and 556w shown in FIG. 12. FIG. 13 also shows the configuration of a part for generating write data of TIC control circuit 562.
TIC control circuit 562 includes a cycle shifting circuit 600 for transferring test data TD less than 7:0 greater than  of eight bits in accordance with test clock signal TCLK. Cycle shifting circuit 600 delays supplied test data TD less than 7:0 greater than  by a predetermined cycle period of test clock signal TCLK and outputs the delayed data.
To TIC control circuit 562, address signal AD less than 12:0 greater than  of 13 bits and spare address space addressing address signal ADsp are applied.
From cycle shifting circuit 600, data Df less than 7:0 greater than  of eight bits is generated in synchronization with test clock signal TCLK.
TIC data path 560e includes drive circuits DRE0 to DRE7 for copying data Df less than 7:0 greater than  to generate data of eight bits, and a driver SDRe for copying 1-bit data Df less than 7 greater than  to generate spare data SD less than 1 greater than .
Drive circuits DRE0 to DRE7 each including drivers of 8 bits generate 8-bit data D less than 64:71 greater than , D less than 72:79 greater than , . . . and D less than 120:127 greater than , respectively. Each of 8-bit data D less than 64:71 greater than , D less than 72:79 greater than , . . . and D less than 120:127 greater than  has the same data pattern as data Df less than 7:0 greater than .
Driver SDRe is formed by a 1-bit drive circuit and generates spare write data SD less than 1 greater than  by buffering data Df less than 7 greater than .
Similarly, TIC data path 560w includes drive circuits DRW0 to DRW7 each for copying data Df less than 7:0 greater than  to generate data of eight bits, and a driver SDRw for buffering data Df less than 7 greater than  to generate spare data SD less than 0 greater than .
Drive circuits DRW0 to DRW7 generate 8-bit data D less than 7:0 greater than , D less than 15:8 greater than , . . . and D less than 63:56 greater than , respectively. Each of 8-bit data generated by TIC data path 560w has the same data pattern.
Data of 128 bits is generated by expanding the bit width of test data TD less than 7:0 greater than , and therefore, the data pattern of the 128-bit data satisfies the following condition;
D less than 8xc2x7n+m greater than =TD less than m greater than ,
wherein n is an integer ranging from 0 to 15 and m is an integer ranging from 0 to 7.
By copying data Df less than 7:0 greater than  in TIC data paths 560e and 560w, 128-bit internal data can be generated from the 8-bit external data and transmitted to the DRAM core, and spare write data SD less than 0 greater than  and SD less than 1 greater than  can be transferred to the DRAM core. Spare write data SD less than 0 greater than  and SD less than 1 greater than  have the same logic level as that of test data TD less than 7 greater than .
FIG. 14 is a diagram schematically showing the configuration of a data reading part of TIC data paths 560e and 560w shown in FIG. 12. Since TIC data paths 560e and 560w have the same configuration, in FIG. 14, the configuration of TIC data path 560w is specifically shown and the configuration of TIC data path 560e is simply shown by blocks.
TIC data path 560w includes: unit processing circuits UPW0 to UPW7 disposed in correspondence to 8-bit data Q less than 7:0 greater than  to Q less than 63:56 greater than , respectively; and a tri-state buffer 600e provided in correspondence to spare read data SQ less than 0 greater than . Unit processing circuits UPW0 to UPW7 have the same configuration and each includes: a tri-state buffer circuit 610 for buffering 8-bit data Q when activated, to generate internal data TQf less than 7:0 greater than ; and a comparing circuit 612 for comparing corresponding 8-bit internal read data with expected value data CMPD less than 7:0 greater than , and outputting 1-bit data indicating the comparison result.
Tri-state buffer circuit 610 is activated by a corresponding selection signal QSEL among 16-bit selection signal QSEL less than 15:0 greater than  generated in accordance with an address signal from TIC control circuit 562. Tri-state buffer 600e is selectively activated in accordance with a selection signal SQSEL less than 0 greater than  from the TIC control circuit.
TIC data path 560e includes: a tri-state buffer circuit 600e provided in correspondence to spare data SQ less than 1 greater than ; and unit processing circuits UPE0 to UPE7 provided in correspondence to 8-bit data Q less than 64:71 greater than  to Q less than 120:127 greater than , respectively. Unit processing circuits UPE0 to UPE7 are also selectively activated in accordance with a corresponding selection signal of 16bit selection signal QSEL less than 15:0 greater than .
Each of unit processing circuits UPE0 to UPE7 includes: a tri-state buffer circuit for buffering 8-bit data when activated, to generate internal read data TQf less than 7:0 greater than ; and comparing circuit 612 for performing a multi-bit test of determining the match/mismatch between expected value data CMPD less than 7:0 greater than  and corresponding data bits and outputting 1-bit signal indicative of a result of comparison.
Comparing circuit 612 compares 8-bit expected value data CMPD less than 7:0 greater than  with corresponding 8-bit data D less than 8xc2x7n+7:8xc2x7n greater than  bit by bit and then compresses the 8-bit signals of the comparison result to a signal Qmbtf less than n greater than  of one bit. A signal Qmbtf less than 15:0 greater than  of 16 bits indicative of a result of comparison from comparing circuit 612 is further compressed by TIC control circuit 562, and multi-bit result indication signal TQmbt of one bit is generated and transferred to the external tester. At the time of compression, whether the logic level of each bit in 16bit signal Qmbtf less than 15:0 greater than  indicates a match state or not is simply determined (AND operation is performed).
FIG. 15 is a diagram schematically showing the configuration of a part for generating a selection signal shown in FIG. 14 of TIC control circuit 562. In FIG. 15, TIC control circuit 562 includes: a flip flop circuit 620 for transferring address signals AD less than 12:0 greater than  and ADsp synchronously with test clock signal TCLK and generating internal address signals intAD less than 12:0 greater than  and intADsp; a flip flop circuit 621 for transferring internal address signals intAD less than 12:0 greater than  and intADsp from flip flop circuit 620 synchronously with test clock signal TCLK and generating row address signal RA less than 12:0 greater than  and spare row addressing address signal RAsp; a flip flop circuit 622 for transferring address signal intAD less than 3:0 greater than  of four bits from flip flop circuit 620 synchronously with test dock signal TCLK and generating column address signal CA less than 3:0 greater than ; cascaded flip flop circuits 623 to 625 of three stages for transferring internal address signals intAD less than 9:6 greater than  of four bits and intADsp from flip flop circuit 620; and a decoder 626 for decoding an output signal of flip flop circuit 625 and generating selection signals QSEL less than 15:0 greater than  and SQSEL less than 1:0 greater than .
Flip flop circuits 623 to 625 of three stages are disposed in the preceding stage of decoder 626 in order to delay the output signal of decoder 626 by a period corresponding to latency in reading test data. The latency indicates the time period required since a read operation instruction signal instructing data reading is supplied from test interface circuit 512 to DRAM core 510 until test data is read from DRAM core 510 and transferred to test interface circuit 512. Here, it is assumed that the latency is 2.
Each of flip flop circuits 620 to 625 takes in and outputs a received signal synchronously with the rising edge of test clock signal TCLK.
FIG. 16 is a timing chart representing operations in reading test data of the DRAM macro shown in FIGS. 12 to 15. Referring to FIG. 16, the operation of reading test data of the DRAM macro will be described below.
Test interface circuit (TIC) 512 delays the control signals externally applied by one clock cycle of test clock signal TCLK and transfers the control signals to DRAM core 510. Therefore, DRAM core 510 takes in the control signal and an address signal at the rising edge of test clock signal TCLK and executes an internal operation after two cycles when the control signals and others are applied from the tester to test interface circuit 512. It is assumed in FIG. 16 that clock signal CLK and test clock signal TCLK supplied to DRAM core 510 are the signals having the same waveform.
At time T1, a control signal instructing row activation, ACT is supplied to test interface circuit 512 and, at the same time, a row address signal RA(k) of 13 bits is applied. Test interface circuit (TIC) 512 decodes the control signals externally applied and transfers row activating signal /ACT to DRAM core 510 synchronously with the rising edge of clock signal TCLK in accordance with a result of the decoding. As shown in FIGS. 10 and 11, the control signals applied to DRAM core 510 are each a signal of negative logic. In FIG. 16, operation mode instruction signals are indicated by mnemonic codes shown in FIG. 11.
As shown in FIG. 15, row address signal RA(k) is transferred from flip flop circuit 621 synchronously with the rising edge of test clock signal TCLK.
In DRAM core 510, at time T3, row activating signal ACT is taken in together with row address signal RA(k) synchronously with the rising edge of clock signal CLK and a row selecting operation is internally executed.
At time T2, a write operation instruction signal instructing data writing is supplied together with column address signal CA(m) and test data TD(m) to test interface circuit (TIC) 512. Synchronously with the rising edge of test clock signal TCLK, the control signal, column address signal and test data are taken in by test interface circuit (TIC) 512.
In test interface circuit (TIC) 512, control signal decoding operation is performed. Synchronously with the rising edge of dock signal TCLK at time T3, write operation instruction signal WRITE for DRAM core 510, column address signal CA(m) and test data TD(m) are transferred to DRAM core 510.
In DRAM core 510, synchronously with the rising edge of clock signal CLK at time T4, write operation instruction signal WRITE, column address signal CA(m) and data D(m) are taken in, a column selecting operation is executed, and data D(m) of 128 bits are written into the columns designated by column address CA(m).
At time T3, a command (READ) instructing data reading is supplied together with column address signal CA(n) and test data TD(n) to test interface circuit (TIC) 512. Test data TD(n) at the time of data reading is used as expected value data CMPD less than 7:0 greater than  for performing comparison in a data path of test interface circuit 512.
Test data TD(n) supplied to test interface circuit (TIC) 512 at time T3 are not transferred to DRAM core 510 because data writing is not performed in the TIC data path. Particularly, according to the timings shown in FIG. 16, the comparison data (expected value data) is generated by internally shifting data supplied from the external tester by a predetermined cycle period in consideration of column latency at the time of data reading, and is applied to comparing circuit 612 provided in test interface circuit (TIC) 512. Therefore, in receiving comparison data, write data to be written in accordance with the write command is transferred within test interface circuit (TIC) 512 and transferred to the DRAM core. Consequently, even when write data is supplied together with the read command to test interface circuit (TIC) 512, no problem arises.
However, where comparison data CMPD less than 7:0 greater than  is required to be inputted in a cycle earlier than application of the read command due to limitations of the number of delay stages for internally generating comparison data, there occurs such a limitation that the writing operation cannot be performed in the cycle of inputting the comparison data.
The command (READ) supplied to test interface circuit (TIC) 512 at time T3 is decoded in test interface circuit (TIC) 512, read operation instruction signal READ is generated, and read operation instruction signal READ and column address signal CA(n) are supplied to DRAM core 510 synchronously with the rising edge of test clock signal TCLK at time T4. The term xe2x80x9ccommandxe2x80x9d is used as indicating an operation mode instruction provided by a combination of a plurality of control signals represented by the mnemonic codes of FIG. 11.
In DRAM core 510, synchronously with the rising edge of clock signal CLK at time T5, a column selecting operation is started in accordance with read operation instruction signal READ (/RE) and column address signal CA(n), and test data is read internally.
At time T4, a control signal (PRE) instructing precharging operation is supplied to test interface circuit (TIC) 512 and decoded in test interface circuit (TIC) 512, and row inactivating signal PRE is generated and transferred to DRAM core 510. At time T6, row inactivating signal PRE is taken in by DRAM core 510 and the internal precharging operation is executed.
In DRAM core 510, column latency is two cycles, data internally read in accordance with read operation instruction signal READ supplied at time T5 is read in a clock cycle starting at time T6, and read data Q(n) is applied to test interface circuit (TIC) 512.
In test interface circuit (TIC) 512, in the clock cycle starting at time T6, buffer circuit 610 is selectively activated in accordance with a selection signal from decoder 626 shown in FIG. 15, 8-bit data is generated from data Q(n) of 128 bits transferred from DRAM core 510, and comparing circuit 612 compares data TD(n) taken in at time T3 and the read data and generates a signal indicative of the comparison result. Generation of the 8-bit data and the comparison result indication signal are completed by time T7.
In a clock cycle starting at time T7, test interface circuit (TIC) 512 outputs 8-bit test data TQ(n) together with multi-bit test result indication signal Qmbt(n). Decoder 626 and flip flop circuits 620 to 625 shown in FIG. 15 always operate synchronously with test clock signal TCLK. Therefore, by sequentially applying address signals intAD less than 9:6 greater than  and ADsp shown in FIG. 15 in each clock cycle, 8-bit data is sequentially selected in accordance with selection signals QSEL less than 15:0 greater than  and SQSEL less than 1:0 greater than  outputted from decoder 626, and read from test interface circuit (TIC) 512.
Alternatively, decoder 626 may include an address counter for internally performing a counting operation synchronously with test clock signal TCLK, to generate a column address, and decodes the column address to generate selection signal QSEL less than 15:0 greater than .
In the external tester, when multi-bit test result indication signal Qmbt(n) (TQmbt) indicates the mismatch with respect to 8-bit test data TQ(n), test expected value data TD(n) and test read data TQ(n) is compared with each other bit by bit on the 8-bit data basis, thereby identifying the position of a defective memory cell. Multi-bit result indication signal TQmbt is a signal indicative of match/mismatch of 128-bit data simultaneously selected. When multi-bit test result indication signal Qmbt(n) indicates matching, it is determined that all bits of 128-bit test data TQ(n) are non-defective.
The external tester is not required to identify the position of a defective memory cell with respect to all of 8 bits for each 8-bit test data, so that the test time is shortened.
By using test interface circuit 512 as described above, whether a memory cell is defective can be determined by accessing DRAM core 510 externally.
The test of DRAM core 510 includes, other than the above, measurement of setup time, hold time, access time and others. Conventionally, a test with respect to timing relationship of the signals of such a DRAM core 510 is performed as follows.
FIG. 17 is a block diagram schematically showing the relation of input/output signals of test interface circuit 512 and DRAM core 510. In FIG. 17, test interface circuit (TIC) 512 includes: a flip flop circuit 700 for taking in and transferring a TIC input signal synchronously with the rising edge of test clock signal TCLK; an input interface converting logic 702 for converting a signal/data from flip flop circuit 700 into a signal/data according to the interface of the DRAM core; and a flip flop circuit 704 for taking in and transferring an output signal/data of input interface converting logic 702 synchronously with the rising edge of test clock signal TCLK.
The TIC input signal includes test write data, an address signal and a control signal (command) supplied from the external tester. Input interface converting logic 702 includes a circuit of expanding bit width of test write data, and a decoder for decoding a command and generating an operation mode instruction signal to the DRAM core. Therefore, flip flop circuit 700 includes flip flop circuit 620 shown in FIG. 15, and flip flop circuit 704 includes flip flop circuits 621 and 622 shown in FIG. 15.
Test interface circuit (TIC) 512 further includes: an output interface converting logic 706 for converting a signal (read data RD) from DRAM core 510 into data/a signal according to an output interface; and a flip flop circuit 708 for taking in and transferring an output signal/data of output interface converting logic 706 synchronously with test clock signal TCLK and generating a TIC output signal.
Output interface converting logic 706 includes a circuit portion for generating output data TQ less than 7:0 greater than  and multi-bit test result indication signal TQmbt in the TIC data path and TIC control circuit 562 shown in FIG. 14.
Test interface circuit (TIC) 512 further includes a flip flop 710 for taking in and transferring data read from the DRAM core in accordance with latch timing signal MLAT from the external tester. An output signal QLAT from flip flop 710 is supplied to the tester and whether data is accurately read or not is determined.
In the signal/data input portion of DRAM core 510, a flip flop circuit 720 for taking in a signal/data supplied synchronously with the rising edge of clock signal CLK is provided. In the data output portion, a flip flop circuit 725 for outputting data synchronously with clock signal CLK is provided. The setup/hold time of the signal/data in DRAM core 510 is measured by using the rising edge clock signal CLK supplied to flip flop circuit 720. Access time is represented by the time required for a core output signal (read data RD) read from flip flop 725 to reach output interface converting logic 706 of test interface circuit (TIC) 512.
In the case of measuring the setup/hold time, memory write data WD, address signal AD and control signal CTL are transferred from flip flop circuit 704 of test interface circuit (hereinafter, simply referred to as TIC) 512 synchronously with test clock signal TCLK. Consequently, by making the phase of test clock signal TCLK and the phase of clock signal CLK supplied to flip flop circuit 720 shifted from each other, the setup/hold time is measured.
FIG. 18 is a timing chart representing an operation in measuring signal parameters such as setup/hold time and access time. Referring to FIG. 18, the signal parameter measuring operation in test interface circuit 512 shown in FIG. 17 will be described below.
In measuring the setup/hold time, as shown by a waveform SHM in FIG. 18, the phase of test clock signal TCLK is made varied with respect to the phase of clock signal CLK. Specifically, while varying the leading extent of the phase of test clock signal TCLK with respect to the rising edge of clock signal CLK for causing flip flop circuit 720 to take in a signal/data in DRAM core 510, to thereby change setup time, tsu, whether data can be written/read or not accurately is determined. In measuring the setup time, tsu, the setup time of DRAM core 510 is measured in accordance with a binary search method. In measurement of setup time in accordance with the binary search method, the setup time is measured along the following procedure. Specifically, whether DRAM core 510 operates correctly or not is measured by using an intermediate value between the setup time in which all of DRAM cores operate correctly (referred to as maximum measurement value) and the setup time in which all of DRAM cores operate erroneously (referred to as minimum measurement value) as a first setup time measurement value (initial value). When DRAM core 510 operates correctly, DRAM core 510 is operated by using an intermediate value between the initial value and the minimum measurement value as a second measurement value, and whether DRAM core 510 operates correctly or not is measured. According to the measurement result, the next measurement value is set. That is, when DRAM core 510 operates correctly, measurement is further performed by using an intermediate value between the second measurement value and the minimum measurement value. If an erroneous operation occurs, measurement is performed by using an intermediate value between the second measurement value and the initial value. In such a manner, the measuring operation is repeatedly executed, a boundary value between the setup time in which DRAM core 510 operates correctly and the setup time in which DRAM core 510 operates erroneously is obtained and is determined to be the setup time of DRAM core 510.
Similar procedure applies to the hold time, th. By delaying the phase of test clock signal TCLK behind clock signal CLK, the hold time, th of a core input signal Cnxe2x88x921 shown in FIG. 18 is changed. Similarly, a phase delay amount of test clock signal TCLK relative to clock signal CLK is adjusted in accordance with the binary search method, and the hold time, th is measured.
In measuring an access time, the transmission time of read data from DRAM core 510 to logic 502 assembled on the same semiconductor substrate has to be measured. In this case, therefore, with respect to a specific bit in read data from flip flop circuit 725 of DRAM core 510, by changing the phase of latch timing signal MLAT from the external tester, whether target data is read or not is measured. Specifically, in FIG. 18, as shown by an waveform ATM, the phase of latch timing signal MLAT is changed with respect to the rising edge of dock signal CLK and whether output data QLAT from flip flop circuit 710 is data Qmxe2x88x921 or Qm is identified. The boundary value between the access time in which target data Qm is correctly read and the access time in which data Qmxe2x88x921 is read is obtained in accordance with the binary search method, thereby measuring the access time of DRAM core 510.
In FIG. 18, clock signals CLK and TCLK are signals having the same waveform. Clock signals CLK and TCLK and latch timing signal MLAT are applied from the external tester. The phase relation of the signals CLK, TCLK and MLAT can be determined by the external tester. The setup time/hold time and access time can be measured in accordance with the binary search method on the basis of a set phase difference.
FIG. 19 is a diagram schematically showing transfer paths of the signals CLK, TCLK and MLAT between a tester 750 provided externally and DRAM-embedded system LSI (semiconductor integrated circuit device) 500. In FIG. 19, in system LSI 500, clock signal CLK, test clock signal TCLK and latch timing signal MLAT are received via pads 760a, 760b and 760c, respectively. Clock signal CLK supplied to pad 760a is transferred to DRAM core 510 via an internal line 762a. Test clock signal TCLK supplied to pad 760b is transferred to test interface circuit (TIC) 512 via an internal line 762b. Latch timing signal MLAT transferred to pad 760c is transferred to test interface circuit 512 via an internal line 762c. 
Since internal lines 762a, 762b and 762c are different in length and load, and therefore, also different in signal propagation delay amount. Pads 760a, 760b and 760c are connected to a lead frame via bonding wires at the time of packaging. Therefore, where the wiring lengths between the lead frame and pads 760a, 760b and 760c are different, similarly, signal propagation delay amounts are different from each other.
Consequently, the relative timing relationship of the signals CLK, TCLK and MLAT in the system LSI becomes different from the relationship at the time of setting in the external tester due to various signal propagation delay amounts in system LSI 500. It causes a problem such that accurate setup time, hold time and access time cannot be measured in the external tester.
As shown in FIG. 20, for example, when the phase of an internal waveform is deviated due to a deviation of signal propagation delay, in order to make correction of the phase deviation to the set phase change amount Tset of the test clock signal TCLK relative to clock signal CLK, it is required to measure the internal signal waveform using an apparatus such as an oscilloscope for measuring a correction value in advance. However, even when a correction value is measured with respect to one device, the correction value cannot be used for a device of another kind having a different user logic and a different pad layout or frame. Even in a device of the same kind, there is the possibility that the correction value measured with respect to one device cannot be used due to variations in resistance value and capacitance value of an internal line in fabrication process.
After packaging with a mold resin or the like, the internal waveform cannot be monitored at all, so that the correction value itself cannot be measured.
Particularly, in the case of operation synchronized with a high-speed clock signal requiring a more severe specification condition, if the setup time, the hold time and the access time cannot be measured with high precision, a defective device cannot be screened by a DRAM macro sole test. In this case, a defective DRAM macro is assembled in a final product, and such problems arise that the yield in final product test reduces and a product cost increases.
An object of the present invention is to provide a semiconductor circuit device capable of measuring an internal signal timing of an embedded clock synchronous memory with high precision.
Another object of the present invention is to provide a test interface circuit capable of accurately measuring setup/hold time or access time of an embedded memory.
Still another object of the present invention is to provide a test interface circuit capable of screening a defective embedded DRAM core with high precision, thereby improving the yield of a final product.
A semiconductor circuit device according to a first aspect of the present invention includes: a memory core operating synchronously with a memory clock signal; a memory transferring circuit for transferring a signal/data to the memory core synchronously with a test clock signal; a timing selecting circuit receiving at least the memory clock signal and the test clock signal, and selecting one of the memory clock signal and test clock signal; and a timing transferring circuit for taking in and transferring externally an output signal of the timing selecting circuit synchronously with a correcting test clock signal.
A semiconductor circuit device according to a second aspect of the present invention includes: a memory core taking in supplied data synchronously with a memory clock signal; a memory transferring circuit for transferring multi-bit data to the memory core; a replica circuit having the same data transfer characteristics as the memory transferring circuit; a test data selecting circuit for selecting one of the memory clock signal and an output signal of the replica circuit; and a test data transferring circuit for transferring an output signal of the test data selecting circuit synchronously with a correcting test clock signal.
A semiconductor circuit device according to a third aspect of the present invention includes: a memory core operating synchronously with a memory clock signal; a latch transferring circuit for taking in and transferring externally a signal transferred from the memory core synchronously with a latch timing signal; and a test transferring circuit for selecting one of the memory clock signal and the latch timing signal in accordance with a selection signal, and externally transferring that selected signal synchronously with a correcting clock signal.
By selecting one of the memory clock signal and the test clock signal and transferring the selected clock signal synchronously with the correcting clock signal, the phase of the test clock signal or memory clock signal relative to the phase of the correcting clock signal can be detected by the external tester, and the phase difference between the memory clock signal and the test clock signal can be accordingly detected. By using the phase difference, a measurement value of setup time, the hold time or the access time can be corrected, and the setup time, the hold time or the access time can be measured with high precision.
By selectively transferring an output signal of a replica circuit having the same transfer characteristic as that of a data transferring circuit and a memory clock signal synchronously with a clock signal for correction, the phase difference between write data and the memory clock signal can be detected by using the clock signal for correction as a reference by the external tester. Thus, setup time and hold time of the write data can be corrected with high precision, and the setup time or hold time can be accordingly measured with high precision.
By transferring one of the latch timing signal and the memory clock signal synchronously with the correcting clock signal, the phase difference between the latch timing signal and the memory clock signal can be detected, a measured access time value can be accurately corrected, and accurate access time can be determined.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.